This invention relates to circuits and methods for increasing drive strength and reducing propagation delays of a digital logic circuit. More particularly, this invention relates to circuits and methods for increasing drive strength and reducing propagation delays of a digital logic circuit through the use of feedback.
Drive strength of a digital logic circuit is a measure of the relative ability of that circuit to transition digital states. In particular, for an output signal voltage transition from a digital “1” to a digital “0”, a digital logic circuit having high drive strength sources significant drive current that charges the output load capacitance of that circuit to a digital “1”. Alternatively, for an output signal voltage transition from a digital “1” to a digital “0”, a digital logic circuit having high drive strength sources significant drive current that discharges the output load capacitance of that circuit to a digital “0”.
Because charging the output load capacitance requires a non-zero rise time, and because discharging the output load capacitance requires a non-zero fall time, digital logic circuits do not transition digital states instantaneously. Propagation delay is the time required for the output signal voltage of a digital logic circuit to transition digital states responsive to an input signal voltage transition. In particular, propagation delay for an output signal voltage transition from a digital “1” to a digital “0” is the time required to discharge the output load capacitance to a digital “0” responsive to an input signal voltage transition. Alternatively, propagation delay for an output signal voltage transition from a digital “0” to a digital “1”, is the time required to charge the output load capacitance to a digital “1” responsive to an input signal voltage transition. Because transition times (i.e., rise time and fall time) of a digital logic circuit are inversely proportional to the drive strength (i.e., the amount of available drive current) of that circuit, digital logic circuits having higher drive strength generally exhibit advantageously lower propagation delays than digital logic circuits having lower drive strength.
Digital logic circuits having lower propagation delays have advantageously higher data throughput capability. In particular, because a digital logic circuit having lower propagation delays transitions digital states more quickly than a digital logic circuit having higher propagation delays, digital logic circuits having lower propagation delays can operate at desirably higher operating frequencies (which allow higher data throughput).
Further, as the complexity of integrated circuits continues to increase, a digital logic circuit is often required to drive an increased number of load devices (i.e., increased fan-out). Digital logic circuits having higher drive strength can advantageously drive a higher number of load devices than a digital logic circuit having lower drive strength.
In view of the foregoing, it would be desirable to provide circuits and methods for increasing drive strength and reducing propagation delays of a digital logic circuit.